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PRELIMINARY CM2006 VGA Port Companion Circuit For Monitors
Features
* * * * Includes ESD protection, level-shifting, buffering and sync impedance matching VESA VSIS Version 1 Revision 2 Compatible Interface Supports Optional NAVI Signalling requirements 7 channels of ESD protection for all VGA port connector pins meeting IEC-61000-4-2 Level 4 ESD requirements (8kV contact discharge) Very low loading capacitance from ESD protection diodes on VIDEO lines, 3pF maximum Schmitt triggered input buffers for HSYNC and VSYNC lines Bi-directional level shifting N-channel FETs provided for DDC_CLK & DDC_DATA channels Backdrive protection on all lines Compact 16-lead QSOP package
Product Description
The CM2006 connects between the VGA or DVI-I port connector and the internal analog or digital flat panel controller logic. The CM2006 incorporates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the video, DDC and SYNC lines is implemented with low-capacitance current steering diodes. All connector interface pins are designed to safely handle the high current spikes specified by IEC-61000-4-2 Level 4 (8kV contact discharge). The ESD protection for the DDC, SYNC and VIDEO signal pins is designed to prevent "back current" when the device is powered down while connected to a video source that is powered up. Separate positive supply rails are provided for the VIDEO / SYNC signals and DDC signals to facilitate interfacing with low voltage video controller ICs and microcontrollers to provide design flexibility in multisupply-voltage environments. Two Schmitt-Triggered non-inverting buffers redrive and condition the HSYNC and VSYNC signals from the video Connector (SYNC1, SYNC2). These buffers accept VESA VSIS compliant TTL input signals and convert them to CMOS output levels that swing between Ground and VCC. (cont'd next page)
* * * * *
Applications
* VGA and DVI-I ports in: - Monitors - Set Top Boxes
Simplified Electrical Schematic
VCC_DDC BYP
8 7
VCC
1 10 11
DDC_OUT1 DDC_OUT2
VIDEO_1 VIDEO_2 VIDEO_3 GND
3 4 5 6 16 9 12 2 13 15 14
RT RT
GND
DDC_IN1 DDC_IN2 ENABLE SYNC_IN1 SYNC_IN2
SYNC_OUT2 SYNC_OUT1
(c) 2006 California Micro Devices Corp. All rights reserved. 02/21/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
1
PRELIMINARY CM2006
Product Description (cont'd)
Two N-channel MOSFETs provide the level shifting function required when the DDC controller or EDID EEPROM is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS (VCC_DDC) should be connected to the supply rail (typically 3.3V, 2.5V etc.) that supplies power to the transceivers of the DDC controller.
PACKAGE / PINOUT DIAGRAM
Top View
VCC ENABLE VIDEO_1 VIDEO_2 VIDEO_3 GND VCC_DDC BYP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SYNC_OUT2 SYNC_IN2 SYNC_OUT1 SYNC_IN1 DDC_IN2 DDC_OUT2 DDC_OUT1 DDC_IN1
Note: This drawing is not to scale.
16 Pin QSOP
PIN DESCRIPTIONS
LEAD(s) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NAME VCC ENABLE VIDEO_1 VIDEO_2 VIDEO_3 GND VCC_DDC BYP DDC_IN1 DDC_OUT1 DDC_OUT DDC_IN2 SYNC_IN1 SYNC_OUT1 SYNC_IN2 SYNC_OUT2
DESCRIPTION This is a supply input for the SYNC_1 and SYNC_2 level shifters, video protection and the DDC circuits. Active high enable. Disables the Sync buffer outputs when low. Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. Ground reference supply pin. This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates. An external 0.22uF bypass capacitor is required on this pin. DDC signal input. Connects to the video connector side of one of the DDC lines.signal output. DDC signal output. Connects to the monitor DDC logic. DDC signal output. Connects to the monitor DDC logic. DDC signal input. Connects to the video connector side of one of the DDC lines Sync signal buffer input. Connects to the video connector side of one of the sync lines. Sync signal buffer output. Connects to the monitor SYNC logic. Sync signal buffer input. Connects to the video connector side of one of the sync lines. Sync signal buffer output. Connects to the monitor SYNC logic.
(c) 2006 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
02/21/06
PRELIMINARY CM2006
Ordering Information
PART NUMBERING INFORMATION
Standard Finish Pins 16 Package QSOP Ordering Part Number1 CM2006-02QS Part Marking CM2006-02QS Lead-free Finish Ordering Part Number1 CM2006-02QR Part Marking CM2006-02QR
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER VCC_DDC and VCC Supply Voltage Inputs DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 DDC_IN1, DDC_IN2 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2, ENABLE Operating Temperature Range Storage Temperature Range Package Power Rating (TA=25C) RATING [GND - 0.5] to +6.0 [GND - 0.5] to [VCC + 0.5] [GND - 0.5] to 6.0 [GND - 0.5] to 6.0 [GND - 0.5] to [VCC + 0.5] -40 to +85 -40 to +150 500 UNITS V V V V V C C mW
STANDARD OPERATING CONDITIONS
PARAMETER Operating Temperature Range VCC RATING -40 to +85 5 UNITS C V
(c) 2006 California Micro Devices Corp. All rights reserved. 02/21/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
3
PRELIMINARY CM2006
Specifications
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL ICC_DDC ICC PARAMETER VCC_DDC Supply Current VCC Supply Current CONDITIONS VCC_DDC = 5.0V VCC = 5V; SYNC inputs at GND or VCC; SYNC outputs unloaded VCC = 5V; SYNC inputs at 3.0V; SYNC outputs unloaded VF VIH VIL VHYS VOH VOL ROUT IIN ESD Diode Forward Voltage Logic High Input Voltage Logic Low Input Voltage Hysteresis Voltage Logic High Output Voltage Logic Low Output Voltage SYNC Driver Output Resistance Input Current VIDEO Inputs SYNC_IN1, SYNC_IN2 Inputs IOFF Level Shifting N-MOSFET "OFF" State Leakage Current IF = 10mA VCC = 5.0V; Note 2 VCC = 5.0V; Note 2 VCC = 5.0V; Note 2 IOH = 0mA, VCC = 5.0V; Note 2 IOL = 0mA, VCC = 5.0V; Note 2 VCC = 5.0V; SYNC Inputs at GND or 3.0V VCC = 5.0V; VIN = VCC or GND VCC = 5.0V; VIN = VCC or GND (VCC_DDC - VDDC_IN) < 0.4V; VDDC_OUT = VCC_DDC (VCC_DDC - VDDC_OUT) < 0.4V; VDDC_IN = VCC_DDC 10 0.18 3 3.5 12 12 3 2 8 7 15 4.0 0.15 24 10 10 10 10 400 2.0 0.5 MIN TYP MAX UNITS 10 1 2.0 1.0 A mA mA V V V mV V V A A A A A V pF pF ns ns ns kV kV
IBACKDRIVE Current conducted from input pins when Vcc VCC < VINPUT_PIN ; Note 6 is powered down. VON CIN_VID tPLH tPHL tR, tF VESD1 VESD Voltage Drop Across Level-shifting N-MOSFET when "ON" VIDEO Input Capacitance SYNC Driver L => H Propagation Delay SYNC Driver H => L Propagation Delay SYNC Driver Output Rise & Fall Times ESD Withstand Voltage, Sync_out pins only ESD Withstand Voltage VCC_DDC = 2.5V; VS = GND; IDS = 3mA; VCC = 5.0V; VIN = 2.5V; f = 1MHz; Note 4 VCC = 2.5V; VIN = 1.25V; f = 1MHz; Note 4 CL = 50pF; VCC = 5.0V; Input tR and tF < 5ns CL = 50pF; VCC = 5.0V; Input tR and tF < 5ns CL = 50pF; VCC = 5.0V; Input tR and tF < 5ns VCC = 5V; Notes 3, 4, & 5 VCC = 5V; Notes 3, 4, & 6
Note 1: All parameters specified over standard operating conditions unless otherwise noted Note 2: These parameters apply only to the SYNC drivers. Note that ROUT = RT + RBUFFER. Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. BYP and VCC must be bypassed to GND via a low impedance ground plane with a 0.22F, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulses can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2. All pins are ESD protected to the industry standard 2kV Human Body Model (MIL-STD-883, Method 3015). Note 4: This parameter is guaranteed by design and characterization. Note 5: This specification applies to the SYNC_OUT pins only. Note 6: Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2.
(c) 2006 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
02/21/06
PRELIMINARY CM2006
Application Information
VCC_5V
Optional EMI Filters
VSYNC HSYNC
C11
FB4
C12
0.22uF
VSYNC
ENABLE VCC
C9
FB3
C10
HSYNC
SYNC_IN1 SYNC_OUT1
DDCA_CLK DDCA_DATA
C7
FB2
C8
SYNC_IN2 SYNC_OUT2 DDC_IN1 DDC_OUT1 DDC_OUT2
R
R
DDC_CLK DDC_DATA
C5
FB1
C6
DDC_IN2
CM2006
RED_VIDEO GREEN_VIDEO BLUE_VIDEO
VF** VF** VF**
** VIDEO Filters.
VIDEO_1 VIDEO_2 VIDEO_3 VCC_DDC
BYP
0.22uF
RED GREEN BLUE
75 75 75
Video Port Connector
VCC_GPIO
Figure 1. Typical Application Connection Diagram
NOTES 1 The CM2006 should be placed as close to the VGA or DVI-I connector as possible. 2 The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B signals. 3 If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with external 37.5 ohm resistors. 4 "VF" are external video filters for the RGB signals. 5 Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins. Connections to the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than 5mm) for best ESD protection. 6 The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum ESD withstand voltage at the DDC_OUT pins from 8kV to 2kV. If 8kV ESD protection is required, a 0.22F ceramic bypass capacitor should be connected between BYP and ground. 7 The SYNC buffers may be used interchangeably between HSYNC and VSYNC. 8 The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference only. The component values and filter configuration may be changed to suit the application. 9 The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA. 10 R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when no monitor is connected to the VGA connector. If used, it should be noted that "back current" may flow between the DDC pins and VCC_5V via these resistors when VCC_5V is powered down.
(c) 2006 California Micro Devices Corp. All rights reserved. 02/21/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
5
PRELIMINARY CM2006
Mechanical Details
QSOP Mechanical Specifications CM2006 devices are packaged in 16-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-16 package, see the California Micro Devices QSOP Package Information document. Mechanical Package Diagrams
TOP VIEW
D
16 15 14 13 12 11 10 9
PACKAGE DIMENSIONS
Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.35 0.10 0.20 0.18 4.80 3.81 5.79 0.40 Max 1.75 0.25 0.30 0.25 5.00 3.98 6.19 1.27 Min 0.053 0.004 0.008 0.007 0.189 0.150 0.228 0.016 QSOP (JEDEC name is SSOP) 16 Inches Max 0.069 0.010 0.012 0.010 0.197 0.157 0.244 0.050
C
END VIEW SEATING PLANE SIDE VIEW 1 2 3 4 5 6 7 8
H
Pin 1 Marking
E
A B e
A1
0.64 BSC
0.025 BSC
100 pcs* 2500 pcs Controlling dimension: inches
L
* This is an approximate number which may vary.
Package Dimensions for QSOP-16
(c) 2006 California Micro Devices Corp. All rights reserved.
6
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.cmd.com
02/21/06

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